View X20C04_1635247.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

X20C04 1 ?xicor, inc. 1992, 1995, 1996 patents pending characteristics subject to change without notice 3825-2.8 2/24/99 t4/c0/d0 sh nonvolatile static ram description the xicor X20C04 is a 512 x 8 novram featuring a static ram overlaid bit-for-bit with a nonvolatile electri- cally erasable prom (e 2 prom). the X20C04 is fabri- cated with advanced cmos floating gate technology to achieve low power and wide power-supply margin. the X20C04 features the jedec approved pinout for byte- wide memories, compatible with industry standard rams, roms, eproms, and e 2 proms. the novram design allows data to be easily trans- ferred from ram to e 2 prom (store) and e 2 prom to ram (recall). the store operation is completed in 5ms or less and the recall operation is completed in 5s or less. xicor novrams are designed for unlimited write operations to ram, either from the host or recalls from e 2 prom, and a minimum 1,000,000 store operations to the e 2 prom. data retention is specified to be greater than 100 years. features ? high reliability endurance: 1,000,000 nonvolatile store operations retention: 100 years minimum ? power-on recall e 2 prom data automatically recalled into sram upon power-up ? lock out inadvertent store operations ? low power cmos standby: 250a ? infinite e 2 prom array recall, and ram read and write cycles ? compatible with x2004 4k X20C04 512 x 8 bit pin configuration a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 nc nc nc oe nc ce i/o 7 i/o 6 nc ne nc v cc we nc i/o 1 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 4321323130 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 X20C04 (top view) 3825 fhd f03 lcc plcc ne nc a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 v cc we nc a 8 nc nc oe nc ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 X20C04 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 3825 fhd f02 plastic cerdip
X20C04 2 pin descriptions addresses (a 0 Ca 8 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable ( ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, power consumption is reduced. output enable ( oe ) the output enable input controls the data output buffers and is used to initiate read and recall operations. output enable low disables a store operation regardless of the state of ce , we , or ne . data in/data out (i/o 0 Ci/o 7 ) data is written to or read from the X20C04 through the i/o pins. the i/o pins are placed in the high impedance state when either ce or oe is high or when ne is low. write enable ( we ) the write enable input controls the writing of data to both the static ram and stores to the e 2 prom. nonvolatile enable ( ne ) the nonvolatile enable input controls all accesses to the e 2 prom array (store and recall functions). pin names symbol description a 0 Ca 8 address inputs i/o 0 Ci/o 7 data input/output we write enable ce chip enable oe output enable ne nonvolatile enable v cc +5v v ss ground nc no connect 3825 pgm t01 v cc sense row select control logic column select & i/os eeprom array 512 x 8 sram array ce oe we ne a 3 Ca 6 i/o 0 Ci/o 7 a 0 Ca 2 a 7 Ca 8 recall store 3825 fhd f01 functional diagram
X20C04 3 power-up recall upon power-up (v cc ), the X20C04 performs an auto- matic array recall. when v cc minimum is reached, the recall is initiated, regardless of the state of ce , oe , we and ne . write protection the X20C04 has five write protect features that are employed to protect the contents of both the nonvolatile memory and the ram. ?v cc senseall functions are inhibited when v cc is 3.5v. ? a ram write is required before a store cycle is initiated. ? write inhibitholding either oe low, we high, ce high, or ne high during power-up and power- down will prevent an inadvertent store operation. ? noise protectiona combined we , ne , oe and ce pulse of less than 20ns will not initiate a store cycle. ? noise protectiona combined we , ne , oe and ce pulse of less than 20ns will not initiate a recall cycle. device operation the ce , oe , we and ne inputs control the X20C04 operation. the X20C04 byte-wide novram uses a 2-line control architecture to eliminate bus contention in a system environment. the i/o bus will be in a high impedance state when either oe or ce is high, or when ne is low. ram operations ram read and write operations are performed as they would be with any static ram. a read operation requires ce and oe to be low with we and ne high. a write operation requires ce and we to be low with ne high. there is no limit to the number of read or write operations performed to the ram portion of the X20C04. nonvolatile operations with ne low, recall operation is performed in the same manner as ram read operation. a recall operation causes the entire contents of the e 2 prom to be written into the ram array. the time required for the operation to complete is 5s or less. a store operation causes the entire contents of the ram array to be stored in the nonvolatile e 2 prom. the time for the operation to complete is 5ms or less. symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
X20C04 4 absolute maximum ratings* temperature under bias .................. C65c to +135c storage temperature ....................... C65c to +150c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current ........................................... 10ma lead temperature (soldering, 10 seconds) ..... 300c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc current (active) 100 ma ne = we = v ih , ce = oe = v il address inputs = 0.4v/2.4v levels @ f = 5mhz. all i/os = open i cc2 v cc current during store 10 ma all inputs = v ih all i/os = open i sb1 v cc standby current 10 ma ce = v ih (ttl input) all other inputs = v ih , all i/os = open i sb2 v cc standby current 250 a all inputs = v cc C 0.3v (cmos input) all i/os = open i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc , ce = v ih v il (1) input low voltage C1 0.8 v v ih (1) input high voltage 2 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage 2.4 v i oh = C400a 3825 pgm t04.3 power-up timing symbol parameter max. units t pur (2) power-up to ram operation 100 s t puw (2) power-up to nonvolatile operation 5 ms 3825 pgm t05 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. capacitance t a = +25c, f = 1mhz, v cc = 5v. symbol test max. units conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 6 pf v in = 0v 3825 pgm t06.1 recommended operating conditions temperature min. max. commercial 0c +70c industrial C40c +85c military C55c +125c 3825 pgm t02.1 supply voltage limits X20C04 5v 10% 3825 pgm t03
X20C04 5 5v 1.92k w 1.37k w output 100pf endurance and data retention parameter min. units endurance 100,000 data changes per bit store cycles 1,000,000 store cycles data retention 100 years 3825 pgm t07.1 equivalent a.c. load circuit a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v 3825 pgm t08.2 3825 fhd f04.1 mode selection ce we ne oe mode i/o power h x x x not selected output high z standby l h h l read ram output data active l l h h write 1 ram input data high active l l h h write 0 ram input data low active l h l l array recall output high z active l l l h nonvolatile storing output high z active l h h h output disabled output high z active l l l l not allowed output high z active l h l h no operation output high z active 3825 pgm t09.1
X20C04 6 a.c. characteristics (over the recommended operating conditions unless otherwise specified) read cycle limits X20C04-15 X20C04-20 X20C04-25 X20C04 symbol parameter min. max. min. max. min. max. min. max. units t rc read cycle time 150 200 250 300 ns t ce chip enable access time 150 200 250 300 ns t aa address access time 150 200 250 300 ns t oe output enable access time 50 70 100 150 ns t lz (3) chip enable to output in low z 0 0 0 0 ns t olz (3) output enable to output in low z 0 0 0 0 ns t hz (3) chip disable to output in high z 80 100 100 100 ns t ohz (3) output disable to output in high z 80 100 100 100 ns t oh output hold from address change 0 0 0 0 ns 3825 pgm t10 read cycle 3825 fhd f05 note: (3) t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf from the point when ce or oe return high (whichever occurs first) to the time when the outptus are no longer driven. t ce t rc address ce oe we data valid data valid t oe t lz t olz t oh t aa t hz t ohz data i/o t oe v ih
X20C04 7 we controlled write cycle write cycle limits X20C04-15 X20C04-20 X20C04-25 X20C04 symbol parameter min. max. min. max. min. max. min. max. units t wc write cycle time 150 200 250 300 ns t cw chip enable to end of write input 150 200 250 300 ns t as address setup time 0 0 0 0 ns t wp write pulse width 100 120 150 200 ns t wr write recovery time 0 0 0 0 ns t dw data setup to end of write 100 120 150 200 ns t dh data hold time 0 0 0 0 ns t wz (4) write enable to output in high z 80 100 100 100 ns t ow (4) output active from end of write 5 5 5 5 ns t oz (4) output enable to output in high z 80 100 100 100 ns 3825 pgm t11 t wc t cw t as t oz t wp t dw t dh t ow t wr data valid address oe ce we data out data in 3825 fhd f06 note: (4) t wz , t ow , and t oz are periodically sampled and not 100% tested.
X20C04 8 3825 fhd f07.1 t wc t cw t as t wp t dw t dh t wr data valid address oe ce we data out data in t wz t ow v ih ce controlled write cycle
X20C04 9 oe we ce data i/o t stc t sp t oest t nhz t ns ne v cc v cc min (5) t soe store cycle limits X20C04-15 X20C04-20 X20C04-25 X20C04 symbol parameter min. max. min. max. min. max. min. max. units t stc store cycle time 5 5 5 5 ms t sp store pulse width 100 120 150 200 ns t nhz nonvolatile enable to 80 100 100 100 ns output in high z t oest output enable from 10 10 10 10 ns end of store t soe oe disable to store 20 20 20 20 ns function t ns ne setup time from we 0000ns 3825 pgm t09 store timing 3825 fhd f15.1 note: (5) X20C04 v cc min. = 4.5v the store pulse width (t sp ) is a minimum time that ne , we and ce must be low simultaneously.
X20C04 10 array recall cycle limits X20C04-15 X20C04-20 X20C04-25 X20C04 symbol parameter min. max. min. max. min. max. min. max. units t rcc array recall cycle time 5 5 5 5 s t rcp (6) recall pulse width to 0.1 1 0.12 1 0.15 1 0.2 1 s initiaterecall t rwe we setup time to ne 000 0 ns 3825 pgm t13.1 array recall cycle address ne oe we ce data i/o t rcc t rcp t rwe 3825 fhd f10 note: (6) the recall pulse width (t rcp ) is a minimum time that ne , oe and ce must be low simultaneously to insure data integrity, ne and ce.
X20C04 11 packaging information 0.620 (15.75) 0.590 (14.99) typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) typ. 0.100 (2.54) 0.023 (0.58) 0.014 (0.36) typ. 0.018 (0.46) 0.060 (1.52) 0.015 (0.38) 3926 fhd f08 pin 1 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.038 (0.97) typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) max. 0.015 (0.38) 0.008 (0.20) 0 15 28-lead hermetic dual in-line package type d note: all dimensions in inches (in parentheses in millimeters) 1.490 (37.85) max. seating plane 0.005 (0.127) min. 0.232 (5.90) max. 0.150 (3.81) min.
X20C04 12 packaging information 3926 fhd f04 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.160 (4.06) 0.120 (3.05) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.470 (37.34) 1.400 (35.56) 1.300 (33.02) ref. pin 1 index 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.510 (12.95) 0.085 (2.16) 0.040 (1.02) 0 15 28-lead plastic dual in-line package type p typ. 0.010 (0.25)
X20C04 13 packaging information 0.150 (3.81) bsc 0.458 (11.63) CC 0.458 (11.63) 0.442 (11.22) pin 1 3926 fhd f14 0.020 (0.51) x 45 ref. 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) typ. (4) plcs. 0.040 (1.02) x 45 ref. typ. (3) plcs. 0.050 (1.27) bsc 0.028 (0.71) 0.022 (0.56) (32) plcs. 0.200 (5.08) bsc 0.558 (14.17) CC 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) pin 1 index corner 32-pad ceramic leadless chip carrier package type e note: 1. all dimensions in inches (in parentheses in millimeters) 2. tolerance: 1% nlt 0.005 (0.127) 0.300 (7.62) bsc 0.015 (0.38) min. 0.400 (10.16) bsc 0.560 (14.22) 0.540 (13.71) dia. 0.015 (0.38) 0.003 (0.08)
X20C04 14 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) typ. typ. 0.017 (0.43) 0.045 (1.14) x 45 0.300 (7.62) ref. 0.453 (11.51) 0.447 (11.35) typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) typ. 0.490 (12.45) pin 1 0.400 (10.16) ref. 0.553 (14.05) 0.547 (13.89) typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) typ. 0.590 (14.99) 3 typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) seating plane 0.004 lead co C planarity 3926 fhd f13 32-lead plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only 0.510" typical 0.050" typical 0.050" typical 0.300" ref footprint 0.400" 0.410" 0.030" typical 32 places
X20C04 15 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. ordering information access time C15 = 150ns C20 = 200ns C25 = 250ns blank = 300ns temperature range blank = commercial = 0c to +70c i = industrial = C40c to +85c m = military = C55c to +125c mb = mil-std-833 package d = 28-lead cerdip p = 28 lead plastic dip e = 32-pad ceramic lcc j = 32-lead plcc device X20C04 x x -x

▲Up To Search▲

Price & Availability of X20C04

	To Download X20C04 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .